Dr. Chandan Bandyopadhyay (HOD)

Associate Professor

About

Email	chandan.bandyopadhyay@bcrec.ac.in
Date of birth	1987-05-05
Date of joining	2022-07-01
Department	Computer Science and Engineering (Data Science)
Address
Vidwan ID
About Me
Specialization / Research Interest	Quantum Computing Design Analysis of Algorithms for Logic Syntheis Optical Circuit Design

Qualifications

Educational Qualifications

Post-Doc
University of Bremen , Germany (listed in top 500 QS World University) - (01/01/2020 – 01/01/2021)
PhD
Indian Institute of Engg. Science andTechnology, Shibpur - (26/07/2013 – 19/09/2019)
M.Tech
Indian Institute of Engg. Science andTechnology, Shibpur - (27/06/2011 – 30/06/2013)

Examination Cleared

GATE

Teaching and R & D experience

Teaching	Research	Industry
More than 10 Years in Teaching Profession	6 Years Experience in Full Time Research

Type of Job/Category: Teaching in Full Time

Position Held: Asst. Professor

Duration: 16 Months

Institution & Department: BCET Durgapur, Dept of CSE(NBA accredited)

Type of Job/Category: Teaching in Full Time

Position Held: Senior Asst. Professor (Grade-I)

Duration: 16Months

Institution & Department: Vellore Institute of Technology(VIT), AP

Type of Job/Category: Teaching inFull Time

Position Held: HoD in CSE(Data Science) &Associate Professor

Duration: Presently serving since 01/07/2022

Institution & Department: Dr. B C. Roy Engg. College, Durgapur

Type of Job/Category: Research in Full Time

Position Held: Junior Research Fellow

Duration: 12 Months

Institution & Department: IIEST, Shibpur, Information Technology

Type of Job/Category: Research inFull Time

Position Held: Council of Scientific & Industrial Research(CSIR)-GoI, New Delhi, Senior Research Fellow

Duration: 48 Months

Institution & Department: IIEST, Shibpur, Dept of Information Technology

Type of Job/Category: Research in Full Time

Position Held: Post-doctoral Researcher

Duration: 12 Months

Institution & Department: University of Bremen, Germany,Dept of CSE

1. Computer Network

2. Compiler Design

3. Database Management System

4. Cryptography

5. Research Methodology (PhD course work paper)

6. Theory of Computation

Quantum Computing

Design Analysis of Algorithms for Logic Syntheis

Optical Circuit Design

1. Received Post Doctoral offer from University of Bremen, Germany in 2019

2. Recipient of Senior Research Fellow award from Council of Science and Industrial Research, Govt. of India, New Delhi in year 2014

3. Awarded with Doctoral Merit Scholarship by Technical Education Quality Improvement Program, World Bank in the year of 2013

4. Obtained Gate Scholarship by Ministry of Human Resource Dept., Govt. of India, New Delhi

5. Has cracked all India entrance Examination “GATE” in Computer Science by scoring above 95 percentile in 2011.

6. Have featured in best 16 research articles surveyed by IIT-Delhi and ACM India council jointly, in 2015-16

7. Recipient of silver medal for being selected as a Topper of the Department while pursuing Bachelor of Technology

8. District topper and State Level participant in Student Science Seminar in the year of 2000, 2001

9. Received best paper award in IEEE TechSym -2017 held at IIT-KGP

10. Has received best presenter award in Indian Institute of Engineering Science & Technology, Shibpurresearch colloquium 2016.

Activities

Publications

Journal

Date	Title	Journal	DOI	Link
08-02-2022	A Novel Heuristic Method for Linear Nearest Neighbour Realization of Reversible Circuits	IETE Journal of Research	DOI	View
11-09-2020	An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture	Integration	DOI	View
27-07-2020	Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures	IETE Journal of Research	DOI	View
26-07-2020	An Approach for Detection and Localization of Missing Gate Faults in Reversible Circuit	IETE Journal of Research	DOI	View
25-07-2020	Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy	Journal of Circuits Systems and Computers	DOI	View
24-07-2020	An Online Testing Scheme for Detection of Gate Faults in ESOP-Based Reversible Circuit	Journal of the Institution of Engineers (India) Series B	DOI	View
23-07-2020	Test Generation from Boolean Generator for Detection of Missing Gate Faults (MGF) in Reversible Circuit Using Boolean Difference Method	IETE Journal of Research	DOI	View
22-07-2020	A template-based technique for efficient Clifford+T-based quantum circuit implementation	Microelectronics Journal	DOI	View
21-07-2020	Improved Designs for All-Optical Adder Circuit Using Mach–Zehnder Interferometers (MZI) Based Optical Components	Journal of the Institution of Engineers (India) Series B	DOI	View
20-07-2020	Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits	IET Computers & Digital Techniques	DOI	View
20-07-2020	Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits	IET Computers & Digital Techniques	DOI	View
19-07-2020	Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures	IET Computers & Digital Techniques	DOI	View
18-07-2020	Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams	Microelectronics Journal	DOI	View
17-07-2020	Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic	Transactions on Computational Science XXIV	DOI	View
01-01-2018	Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams	Microelectronics Journal, Elsevier	DOI	View

Conference

Date	Title	Conference	DOI	Link
08-02-2024	Evolution of 6G- an In-depth Survey on History of Spectrum Allocation	IEEE International Conference on Integrated Intelligence and Communication Systems (ICIICS)	DOI	View
02-04-2024	A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D	23rd International Conference on Embedded Systems (VLSID)	DOI	View
01-05-2014	ESOP-Based Synthesis of Reversible Circuit Using Improved Cube List	IEEE 4th International Symposium on Electronic System Design (ISED)	DOI	View
01-05-2014	Synthesis of ESOP-based reversible logic using negative polarity reed-muller form	IEEE Student Technology Symposium (Tech Sym)-2014	DOI	View
19-06-2014	A transformation based heuristic synthesis approach for reversible circuits	2014 International Conference on Advances in Electrical Engineering (ICAEE)	DOI	View
30-06-2014	A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit	2014 IEEE 44th International Symposium on Multiple-Valued Logic	DOI	View
22-09-2014	Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder	2014 IEEE Computer Society Annual Symposium on VLSI	DOI	View
21-08-2014	All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit	18th International Symposium on VLSI Design and Test	DOI	View
30-07-2015	Diagnosis of SMGF in ESOP Based Reversible Logic Circuit	2014 Fifth International Symposium on Electronic System Design	DOI	View
05-02-2015	All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters	2015 28th International Conference on VLSI Design	DOI	View
17-03-2016	Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library	2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)	DOI	View
29-03-2018	All optical implementation of universal shift-register using terahertz optical asymmetric de-multiplexer based Optical Devices	2018 International Symposium on Devices, Circuits and Systems (ISDCS)	DOI	View
11-12-2024	Secured Home Automation with Voice Recognition Using ML and IoT Devices	2024 IEEE International Conference on Computer Vision and Machine Intelligence (CVMI)	DOI	View
21-07-2016	Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation	2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)	DOI	View
03-11-2016	A synthesis approach for ESOP-based reversible circuit	2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI)	DOI	View

Book Chapters

Date	Title	Book Title	Editor	ISBN	DOI	Link
28-07-2019	Improving the Designs of ESOP-Based Reversible Circuits	Design and Testing of Reversible Logic	Ashutosh Kumar Singh,Masahiro Fujita,Anand Mohan	978-981-13-8820-0	DOI	View
28-07-2019	Detection and Identification of Gate Faults in Reversible Circuit	Design and Testing of Reversible Logic	Prof. Ashutosh Kumar Singh, Dr. Masahiro Fujita, Prof. Anand Mohan	978-981-13-8820-0	DOI	View
28-07-2019	An Efficient Nearest Neighbor Design for 2D Quantum Circuits	Design and Testing of Reversible Logic	Ashutosh Kumar Singh, Masahiro Fujita, Anand Mohan	978-981-13-8820-0	DOI	View

Participations

Participation In Administrative Committees

SL. No.	Post	Committee
1	Exam coordinator	Acted as Exam coordinator in the School of Computer Science (SCOPE) in Vellore Institute of Technology, AP
2	“Microsoft Chapter” coordinator	Served as “Microsoft Chapter” coordinator in Vellore Institute of Technology, AP
3	co- coordinator for ACM chapter	Acted as co- coordinator for ACM chapter in Vellore Institute of Technology, AP

Highlights

Faculty-Details