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Dr. Chandan  Bandyopadhyay (HOD)

Associate Professor

About

chandan.bandyopadhyay@bcrec.ac.in

1987-05-05

2022-07-01

Computer Science and Engineering (Data Science)

Quantum Computing

Design Analysis of Algorithms for Logic Syntheis

Optical Circuit Design

Qualifications

Educational Qualifications
  • Post-Doc
  • University of Bremen , Germany (listed in top 500 QS World University) - (01/01/2020 – 01/01/2021)
  • PhD
  • Indian Institute of Engg. Science andTechnology, Shibpur - (26/07/2013 – 19/09/2019)
  • M.Tech
  • Indian Institute of Engg. Science andTechnology, Shibpur - (27/06/2011 – 30/06/2013)
Examination Cleared
  • GATE
Teaching and R & D experience
Teaching Research Industry
More than 10 Years in Teaching Profession 6 Years Experience in Full Time Research

Type of Job/Category: Teaching in Full Time

Position Held: Asst. Professor

Duration: 16 Months

Institution & Department: BCET Durgapur, Dept of CSE(NBA accredited)

Type of Job/Category: Teaching in Full Time

Position Held: Senior Asst. Professor (Grade-I)

Duration: 16Months

Institution & Department: Vellore Institute of Technology(VIT), AP

Type of Job/Category: Teaching inFull Time

Position Held: HoD in CSE(Data Science) &Associate Professor

Duration: Presently serving since 01/07/2022

Institution & Department: Dr. B C. Roy Engg. College, Durgapur

Type of Job/Category: Research in Full Time

Position Held: Junior Research Fellow

Duration: 12 Months

Institution & Department: IIEST, Shibpur, Information Technology

Type of Job/Category: Research inFull Time

Position Held: Council of Scientific & Industrial Research(CSIR)-GoI, New Delhi, Senior Research Fellow

Duration: 48 Months

Institution & Department: IIEST, Shibpur, Dept of Information Technology

Type of Job/Category: Research in Full Time

Position Held: Post-doctoral Researcher

Duration: 12 Months

Institution & Department: University of Bremen, Germany,Dept of CSE

1. Computer Network

2. Compiler Design

3. Database Management System

4. Cryptography

5. Research Methodology (PhD course work paper)

6. Theory of Computation

Quantum Computing

Design Analysis of Algorithms for Logic Syntheis

Optical Circuit Design

1. Received Post Doctoral offer from University of Bremen, Germany in 2019

2. Recipient of Senior Research Fellow award from Council of Science and Industrial Research, Govt. of India, New Delhi in year 2014

3. Awarded with Doctoral Merit Scholarship by Technical Education Quality Improvement Program, World Bank in the year of 2013

4. Obtained Gate Scholarship by Ministry of Human Resource Dept., Govt. of India, New Delhi

5. Has cracked all India entrance Examination “GATE” in Computer Science by scoring above 95 percentile in 2011.

6. Have featured in best 16 research articles surveyed by IIT-Delhi and ACM India council jointly, in 2015-16

7. Recipient of silver medal for being selected as a Topper of the Department while pursuing Bachelor of Technology

8. District topper and State Level participant in Student Science Seminar in the year of 2000, 2001

9. Received best paper award in IEEE TechSym -2017 held at IIT-KGP

10. Has received best presenter award in Indian Institute of Engineering Science & Technology, Shibpurresearch colloquium 2016.

Activities

Publications

Journal
Year
Journal DOI/Link/Web Link/UGC Link
2015 C. Bandyopadhyay, H. Rahaman, R. Drechsler, “Cube List based Cube Pairing Approach for Synthesis of ESOP based Reversible Logic”, Springer Transactions on Computational Science, 2015, pp. 129-146, Springer, Berlin, Heidelberg DOI
2018 Jan C. Bandyopadhyay, H. Rahaman, R. Wille, R. Drechsler , “Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams. Microelectronics Journal. 2018 Jan 1;71:19-29. DOI
2018 Jul 5 C. Bandyopadhyay, R. Das, A. Chattopadhyay , H. Rahaman, “Design and synthesis of improved reversible circuits using AIG-and MIG-based graph data structures,” IET Computers & Digital Techniques. 2018 Jul 5;13(1):38-48, USA DOI
2018 C. Bandyopadhyay, S. Parekh, H. Rahaman, “An Improved Circuit Synthesis Approach for ESOP-based Reversible Circuit ”IET Computers & Digital Techniques(2018), USA , 12 (4):167 DOI
2018 Oct 1 C. Bandyopadhyay, R. Das, P. Dutta, H. Rahaman“ Improved Designs for All-Optical Adder Circuit Using Mach–Zehnder Interferometers (MZI) Based Optical Components,” Journal of The Institution of Engineers (India): Series B. 2018 Oct 1;99(5):451-65. DOI
2018 Nov 1 L. Biswal, R. Das, C. Bandyopadhyay, H. Rahaman, A. Chattopadhyay “A template-based technique for efficient Clifford +T -based quantum circuit implementation,” Microelectronics Journal. 2018 Nov 1;81:58-68. DOI
2019 Jul 30 B. Mandol, C. Bandyopadhyay,D. Das, D. Kole andH. Rahaman “Test Generation from Boolean Generator for Detection of Missing Gate Faults (MGF) in Reversible Circuit Using Boolean Difference Method,” IETE Journal of Research. 2019 Jul 30:1-7. DOI
2020 Bhattacharjee, A., C.Bandyopadhyay, Ba.Mondal, and H.Rahaman. "Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy." Journal of Circuits, Systems and Computers 29, no. 16 (2020): 2050263. DOI
2020 B. Mandol, C. Bandyopadhyay, A. Bhattacharjee, D. Roy, S. Parekh and H. Rahaman “An approach for Detection and Localization of Missing Gate Faults in Reversible Circuit,” IETE Journal of Research. 2020, pp.1-21 DOI
2020 Bandyopadhyay, C., A.Bhattacharjee, R.Wille, R.Drechsler, and H.Rahaman. "Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures." IETE Journal of Research (2020): 1-14. DOI
2021 Bhattacharjee, A., C.Bandyopadhyay, A. Mukherjee, R.Wille, R.Drechsler, and H.Rahaman. "An ant colony based mapping of quantum circuits to nearest neighbor architectures." Integration 78 (2021): 11-24. DOI
2021 Bhattacharjee, A., Bandyopadhyay, C., Niemann, P., Mondal, B., Drechsler, R. and Rahaman, H., 2021. An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integration, 76,(2021) pp.40-54. DOI
2022 R. Das, C. Bandyopadhyay, H. Rahaman, “An Improved Synthesis Technique for Optical Circuits Using MIG and XMG” Microelectronics Journal. 2022) (SCI Indexed, IF: 1.6)
2022 Bhattacharjee, A., C. Bandyopadhyay, H. Rahaman. " A Novel Heuristic Method for Linear Nearest Neighbor Realization of Reversible Circuits” IETE Journal of Research (2022), SCI Indexed, IF: 1.29)
Conference
Year
Conference National/International DOI/Link/Web Link/UGC Link
2013 C. Bandyopadhyay, D. Roy, D. K. Kole, K. Datta, H. Rahaman, “ESOP-based Synthesis of Reversible Circuit Using Improved Cube list”, IEEE 4th International Symposium on Electronic System Design (ISED), 2013, pp.26-30, Singapore DOI
2014 C. Bandyopadhyay, H. Rahaman, “Synthesis of ESOP-based Reversible Logic using Negative Polarity Reed-Muller Form”, IEEE Student Technology Symposium (Tech Sym)-2014, pp.286 – 291, IIT-KGP, India. DOI
2014 S. Roy, K. Datta, C. Bandyopadhyay, H. Rahaman “A Transformation based Heuristic Synthesis Approach for Reversible Circuits,” IEEE International Conference on Advances in Electrical Engineering 2014,India (pp. 1-5) DOI
2014 C. Bandyopadhyay, and H. Rahaman “Synthesis of ESOP-based Reversible Logic using Positive Polarity Reed-Muller Form”, IEEE Emerging Trends in Computing and Communication (ETCC)-2014, pp. 363-376, Calcutta, India. DOI
2014 C. Bandyopadhyay, H. Rahaman, and R. Drechsler, “A Cube Pairing Approach for Synthesis of ESOP-based Reversible Circuit”, IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL)-2014, pp. 109 - 114, Germany . DOI
2014 P. Dutta, C. Bandyopadhyay, C.Giri, and H. Rahaman “Mach-Zehnder Interferometer based All Optical Reversible Carry-Lookahead Adder”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014, pp. 412 - 417, USA . DOI
2014 P. Dutta, C. Bandyopadhyay, H. Rahaman, “All optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Circuit”, IEEE 18th International Symposium on VLSI Design and Test (VDAT) 2014, pp. 1 - 2, Bangalore . DOI
2014 B. Mandol, C. Bandyopadhyay, D. K. Kole, J. Mathew, H. Rahaman, “Diagnosis of SMGF in ESOP based Reversible Logic Circuit,” IEEE 5th Int’l Symposium on Electronic System Design-2014, pp. 89 - 93, NIT-Suratkal DOI
2014 P. Dutta, C. Bandyopadhyay, H. Rahaman “All optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Counters,” IEEE 28th International Symposium on VLSI Design-2014, pp. 232 - 237, India. (DOI: 10.1109/VLSID.2015.45) DOI
2015 L. Biswal, C. Bandyopadhyay, R. Wille, R. Drechsler H. Rahaman “Improving the Realization of Multiple-Control Toffoli Gates Using NCVW Quantum Gate Library,” IEEE 29th International Conference on VLSI Design-2015, pp. 573 - 574 India, DOI
2016 L. Biswal, C. Bandyopadhyay, A. Chattopadhyay, R. Wille, R. Drechsler and H. Rahaman “Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation” IEEE 46th International Symposium on Multiple-Valued Logic-2016 (ISMVL-2016), pp.156 – 161, Japan DOI
2016 C. Bandyopadhyay, S. Parekh, H. Rahaman, “A Synthesis Approach for ESOP-based Reversible Circuit” IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI-2016), pp. 1741 – 1746, India. DOI
2016 R. Chowdhury,C. Bandyopadhyay, P. Dutta, H. Rahaman, “A Boolean Expression based Template Matching Technique for Optical Circuit Generation” ACM IndiaInternational Conference on Advances in Information Communication Technology & Computing (AICTC-2016), pp. 1– 6,India. DOI
2016 R. Das, C. Bandyopadhyay, P. Dutta, H. Rahaman, “All Optical Reversible Design of Mach-Zehnder Interferometer based Carry-Skip Adder,” IEEE International conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2016), pp: 73 – 78, NIT-Surathkal, India. DOI
2016 B. Mandol, C. Bandyopadhyay, H. Rahaman “Online Testing of SMGF in ESOP Based Reversible Circuit”, IEEE Student Technology Symposium-2016, pp: 141 - 146, IIT-KGP, India. DOI
2016 A. Chakraborty, R. Das, C. Bandopadhyayand H. Rahaman, “BDD based Synthesis Technique for Design of High-Speed Memristor based Circuits,” IEEE 20th International Symposium on VLSI Design and Test-2016, India ,pp. 1-6. DOI
2016 B. Mandol, C. Bandyopadhyay, H. Rahaman “A Testing Scheme for Mixed-Control Based Reversible Circuits”, IEEEInt’l Symposium on Electronic System Design -2016, pp. 96-100, India DOI
2017 N. Chaudhuri, C. Bandopadhyayand H. Rahaman, “Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space,” IEEE 21th International Symposium on VLSI Design and Test-2017, IIT-Roorkee, India,pp. 421-426 DOI
2018 B. Mandol, C. Bandyopadhyay, H. Rahaman “Detection and Localization of Appearance Faults in Reversible Circuits” IEEEInt’l Symposium on Electronic System Design -2018, pp. 1-5, India DOI
2018 A. Manna, S. Saha, R. Das, C. Bandyopadhyay, H. Rahaman “All Optical Design of Cost Efficient Multiplier Circuit Using Terahertz Optical Asymmetric Demultiplexer” IEEEInt’l Symposium on Electronic System Design -2018, pp. 1-5, India DOI
2018 S. Saha, A. Manna, C. Bandyopadhyay, H. Rahaman “All Optical Design of Hybrid Adder Circuit Using Terahertz Optical Asymmetric Demultiplexer” IEEE International Symposium on Devices, Circuits and Systems - 2018, pp. 1-6, India DOI
2018 R. Das,A. Bhattacharjee, L. Biswal C. Bandyopadhyay, H. Rahaman, “All Optical Implementation of Universal Shift-Register Using Terahertz Optical Asymmetric De-multiplexer based Optical Devices,” IEEE International Symposium on Devices, Circuits and Systems - 2018, pp. 1-5, India DOI
2018 A. Bhattacharjee, C. Bandyopadhyay, R. Wille, R. Drechsler, H. Rahaman, “A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018,pp. 305-310,Hong Kong, China DOI
2018 A. Bhattacharjee, C. Bandyopadhyay, H. Rahaman, “A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture” IEEE 22th International Symposium on VLSI Design and Test-2018, pp. 593-605,India. DOI
2019 26. AnirbanBhattacharjee, ChandanBandyopadhyay, Robert Wille, Rolf Drechsler and HafizurRahaman, “Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits,” IEEE 33rd International Conference on VLSI Design-2019, pp. 203-208, India DOI
2018 B. Mandol, A.Bhattacharjee,S. Saha, S. Parekh,C. Bandyopadhyay, H. Rahaman“An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit”IEEE 23rd International Symposium on VLSI Design and Test-2018, pp. 605-616,India. DOI
2020 Bhattacharjee, A., Bandyopadhyay, C., Mondal, B. and Rahaman, H., 2020. A Novel Fault-Detection Scheme for Nearest-Neighbor-Based Reversible Circuits. In Soft Computing: Theories and Applications (pp. 489-500). Springer, 2020, Singapore. DOI
2020 Bhattacharjee, A., Bandyopadhyay, C., Mondal, B. and Rahaman, H., 2020. A survey report on recent progresses in nearest neighbor realization of quantum circuits. In Soft Computing: Theories and Applications (pp. 57-68). Springer, 2020, Singapore. NIT Patna, DOI
2020 Biswal, L., Bandyopadhyay, C. and Rahaman, H., 2020. Clifford+ T-based Fault-Tolerant Quantum Implementation of Code Converter Circuit. In Soft Computing: Theories and Applications (pp. 639-648). Springer, Singapore, 2020NIT Patna, DOI
2021 31. L. Biswal, C. Bandyopadhyay, S. Ghoshand H. Rahaman “Fault-tolerant Implementation of Quantum-Arithmetic and Logical Unit (Q-ALU) using Clifford+T-group”, Springer 1stInternational Conference on Frontiers in Computing and Systems (COMSYS-2021),pp. 833-844. Springer, Singapore, 2021.( DOI:10.1007/978-981-15-7834-2_78) DOI
2019 32. L. Biswal, C. Bandyopadhyay, and H. Rahaman “Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group” IEEE 9th International Symposium on Embedded computing and system Design (ISED 2019), pp. 1-6. IEEE, India, DOI
2020 A.Bhattacharjee, C.Bandyopadhyay, R.Wille, R. Drechsler and H.Rahaman, “Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm” IEEE 50th International Symposium on Multiple-Valued Logic-2020, Japan, pp. 40-45. IEEE, 2020, DOI
2020 34. C. Bandyopadhyay, R. Wille, H. Rahaman, R. Drechsler, “Post Synthesis-Optimization of Reversible Circuit using Template Matching, ”24thIEEE VLSI Design and Test 2020, IIT Bhubaneswar , pp. 1-4. India. DOI
2021 P.Niemann, C.Bandyopadhyay, R.Drechsler: Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. DATE 2021: pp. 200-205, Europe DOI
2022, February Saha, L., Mishra, S. P., Das, D., Kar, U. N., Kumar, A., &Bandyopadhyay, C. (2022, February). A Survey on Optical Circuit Design. In 2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP) (pp. 1-6). IEEE.
2022, July 37. Mondal, B., Kar, U.N., Bandyopadhyay, C., Roy, D. and Rahaman, H., 2022, July. An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. In International Symposium on VLSI Design and Test (pp. 249-261). Cham: Springer Nature Switzerland.
2022, September Das, R., Wary, A., Dey, A., Hazari, R., Bandyopadhyay, C. and Rahaman, H., 2022, September. Design of Optimum n-bit ALU Using Crossbar Gate. In International Conference on Data, Electronics and Computing (pp. 435-444). Singapore: Springer Nature Singapore.
2023 B. Mukhopadhyay, S. Misra, S. Vatsa, S. Bhattacharya, D. Sinha, U.N. Kar, C. Bandyopadhyay "A Blockchain based Networking Approach for Advanced HealthCare Services" ICMLBDA 2023, Springer (Accepted).
2023 40. S.Pal, S.Bhattacharya, B.Mondal, A.Bandyopadhyay, D. Sinha, C. Bandyopadhyay "The Evolutionary Impact of Pattern Recognition in Research Applications – A Wide Spectrum Survey" ICMLBDA 2023, Springer (Accepted).
2023 S. Bhattacharya, A. Mazumder, A.Banerjee, C. Bandyopadhyay "Automated Reviewer Assignment Process using Machine Learning Technique" ICMLBDA 2023, Springer (Accepted).
2023 42. A. Banerjee, A. Mazumder, A. K. Shaw, U. N. Kar, S. Bhattacharya, C. Bandyopadhyay, "Plant Disease Detection Using Modern Deep Learning Approach: YOLOv7" ICMLBDA 2023, Springer (Accepted).
Book Chapter
Year
Book DOI/Link/Web Link/UGC Link
2020 Bandyopadhyay, C., S. Parekh, D. Roy, and H. Rahaman. "Improving the Designs of ESOP-Based Reversible Circuits." In Design and Testing of Reversible Logic, pp. 49-64. Springer, Singapore, 2020. DOI
2020 Mondal, B., C. Bandyopadhyay, A. Bhattacharjee, and H. Rahaman. "Detection and Identification of Gate Faults in Reversible Circuit." In Design and Testing of Reversible Logic, pp. 169-184. Springer, Singapore, 2020. DOI

Participations

Participation In Administrative Committees
SL. No. Post Committee Year
1 Exam coordinator Acted as Exam coordinator in the School of Computer Science (SCOPE) in Vellore Institute of Technology, AP
2 “Microsoft Chapter” coordinator Served as “Microsoft Chapter” coordinator in Vellore Institute of Technology, AP
3 co- coordinator for ACM chapter Acted as co- coordinator for ACM chapter in Vellore Institute of Technology, AP

Thesis Supervised

Patent

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