Dr. ALOKE SAHA

Associate Professor

About

Email	aloke.saha@bcrec.ac.in
Date of birth	1981-01-02
Date of joining	2009-02-26
Department	Electronics and Communication Engineering
Address	Flat-2B; Mira Enclave; Sarat Pally; Fuljhore; Durgapur; West Bengal- 713206
Vidwan ID	184948
About Me
Specialization / Research Interest	Efficient higher-radix and multi-base logic development with unconventional (i.e. MTCMOS, Memristor, CNTFET etc.)/Hybrid strategies for next generation smart processing, Low PDP solution for digital circuits/system, ASIC for data security, Adaptive scalable digital architecture, floating point circuit/system, Reversible Circuit design etc.

Qualifications

Educational Qualifications

PhD
BIT Mesra - 2015
M.E
BIT Mesra - 2006
B.Tech
University of Kalyani - 2003

Examination Cleared

GATE

Teaching and R & D experience

Teaching	Research	Industry
17.5 Years	15.5 Years

Associate Professor at Dr. B. C. Roy Engineering College (01.07.2022 to present)

Assistant Professor (AGP 8000) at Dr. B. C. Roy Engineering College (26.02.2009 to 30.06.2022)

Lecturer at BIT Mesra (16.07.2006 to 25.02.2009)

BE/B.Tech : Digital System Design, CMOS VLSI Design, Analog Electronic Circuits, VLSI Circuit & Systems, EDA for VLSI Design, Embedded System, Basic Electronics, Microelectronics & VLSI Design, Digital Signal Processing, Analog Communication, Microelectronics Engineering, Semiconductor Devices, Pulse & Digital Circuits (PDC)

M.E/M.Tech: Digital IC Design, Processor Architecture for VLSI, Advanced VLSI Design, Mobile communication, Embedded System

Efficient higher-radix and multi-base logic development with unconventional (i.e. MTCMOS, Memristor, CNTFET etc.)/Hybrid strategies for next generation smart processing, Low PDP solution for digital circuits/system, ASIC for data security, Adaptive scalable digital architecture, floating point circuit/system, Reversible Circuit design etc.

Finance-chair: MESIICON 2022, NCETSTEA-2020

Session Chair: ICCDC-2023

Entrepreneurship Week-India 2010 Championship Runner-up by National Entrepreneurship Network, India 2010.

Innovative project award in Master of Engineering by Cadence Design Systems (I) Pvt. Ltd.(Cadence Design Contest 2005-2006)

Activities

Membership of professional bodies

SL. No.	Professional Body
1	Member IEEE (Since 2015): Member Number 93689053 Reviewer (Journal): IET Computer & Digital Technique, IET Circuits Devices & Systems, International Journal of Electronics (IJE)-Taylor & Francis, International Journal of Electronics & Communication (IJEC)-Elsevier, Journal of supercomputing-Springer, Journal of Electrical and Computer Engineering, Journal of Integrated Circuits & Systems etc. Reviewer (Conference) : IEEE International Symposium on Circuits and Systems (ISCAS), International Conference on Communication, Devices & Computing (ICCDC)- Springer, IEEE MESIICON 2022, IEEE NCETSTEA-2020 etc. Technical Committee Member: ICCDC-2023, ICCDC-2021, ICCDC-2019.

SL. No.

Professional Body

Member IEEE (Since 2015): Member Number 93689053 Reviewer (Journal): IET Computer & Digital Technique, IET Circuits Devices & Systems, International Journal of Electronics (IJE)-Taylor & Francis, International Journal of Electronics & Communication (IJEC)-Elsevier, Journal of supercomputing-Springer, Journal of Electrical and Computer Engineering, Journal of Integrated Circuits & Systems etc. Reviewer (Conference) : IEEE International Symposium on Circuits and Systems (ISCAS), International Conference on Communication, Devices & Computing (ICCDC)- Springer, IEEE MESIICON 2022, IEEE NCETSTEA-2020 etc. Technical Committee Member: ICCDC-2023, ICCDC-2021, ICCDC-2019.

Project Ideas Submitted to Govt. Agencies/ On-going Projects / Research Ideas under preparation & execution

SL. No.	Project Ideas Submitted to Govt. Agencies
1	On-going Project: 1. Up-gradation & Modernization of "VLSI Lab (Phase-ll)" to enhance teaching, training and research capabilities in VLSI domain Total Project Cost: Rs. 13,87,500/- Sanctioning Authority/duration: AICTE/2-years

Publications

Journal

Year	Journal	DOI/Link/Web Link/UGC Link
2017	Aloke Saha, Dipankar Pal and Mahesh Chandra, “Benchmarking of DPL Based 8b×8b Novel Wave-Pipelined Multiplier,” Int. J. of Electronics Letters (IJEL), Taylor & Francis, vol.5, no.1, pp.115-128, 2017.	DOI Link
2013	Aloke Saha, Dipankar Pal and Mahesh Chandra, “Low power 6-GHz wave-pipelined 8b×8b multiplier,” IET Circuits, Devices & Systems, vol. 7, no. 3, pp. 124-140, 2013.	DOI Link Web Link
2017	Aloke Saha, Sushil Kumar, Debajit Das and Mrinmoy Chakraborty, “LPHS Logic Evaluation on TSMC 0.18µm CMOS Technology,” International Journal of High Speed Electronics & Systems (IJHSES), World Scientific, vol. 26, no. 4, 2017.	DOI Link
2018	Aloke Saha and Dipankar Pal, “DPL-Based Novel Binary-to-Ternary Converter on CMOS Technology,” AEU-International Journal of Electronics & Communication (IJEC), Elsevier, vol. 92, pp. 69-73, 2018.	DOI Link
2018	Aloke Saha, Rahul Pal, Akhilesh G. Naik and Dipankar Pal, “Novel CMOS Multi-bit Counter for Speed-Power Optimization in Multiplier Design,” AEU-Int. J. of Electronics & Communication (IJEC), Elsevier, vol. 95, pp. 189-198, 2018.	DOI Link
2019	Aloke Saha and Dipanakar Pal, “DPL-Based Novel Time Equalized CMOS Ternary-to-Binary Converter, International Journal of Electronics (IJE), Taylor & Francis, vol.107, no.3, pp. 431-443, 2019.	DOI Link
2020	Aloke Saha and Narendra Deo Singh, “Systematic Design Strategy for DPL-based Ternary Logic Circuit,” International Journal of Nanoparticles (IJNP), Inderscience, vol. 12, no. 1-2, pp. 3-16, 2020.	DOI Link
2020	Aloke Saha, Rahul Pal and Jayanta Ghosh, “Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication,” Micro and Nanosystems, Bentham Sciene Publication, vol.12, no.3, pp. 149-158, 2020.	DOI Link
2021	Aloke Saha, Rakesh Kumar Singh, Pragya Gupta and Dipankar Pal, “DPL-Based Novel CMOS 1-Trit Ternary Full-Adder,” International Journal of Electronics (IJE), Taylor & Francis, vol.108, no.2, pp. 218-236, 2021.	DOI Link
2021	Aloke Saha, Narendra Deo Singh and Dipankar Pal, “Efficient ternary comparator on CMOS technology,” Microelectronics Journal, Elsevier, vol. 109, pp. 105005 (1-9), March 2021.	DOI Link
2022	Aloke Saha, Rakesh Kumar Singh and Dipankar Pal, “Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier,” Microelectronics Journal, Elsevier, vol. 119, pp. 105318 (1-14), January 2022.	DOI Link
2022	Aloke Saha, Rahul Pal, Tripti Kumari, Rakesh Kumar Singh, Somashree Chakraborty and Jayanta Ghosh, “Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer,” Micro and Nanosystems, Bentham Sciene Publication, vol. 14, no. 04, pp. 304-313, May 2022.	DOI Link
2023	Aloke Saha, Rakesh Kumar Singh, Prerona Sanyal & Dipankar Pal, “Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor”, IETE Journal of Research, April 2023.	DOI Link
2023	Aloke Saha, Prerona Sanyal, Deep Narayan Singh, Aastha Bharti and Dipankar Pal, ”Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder,” IETE Journal of Research, October 2023.	DOI Link

Conference

Year	Conference	National/International	DOI/Link/Web Link/UGC Link
2011	A. Saha, D. Pal, Mahesh Chandra and M.K. Goswami, “Novel high speed MCML 8-bit by 8-bit multiplier,” IEEE International Conference on Devices & Communications (ICDeCom-11), BIT Mesra, India, pp. 1-5, 24-25 February 2011,	International	DOI Link
2017	Aloke Saha and Mrinmoy Chakraborty, “Study on LP-HS Logic for High Performance Digital Applications,” IEEE International Conference on Devices for Integrated Circuits (DevIC-2017), KGEC Kalyani, pp. 376-379, 23-24 March 2017	International	DOI Link
2018	Narendra Deo Singh, Rakesh Kumar Singh, Rahul Raj, Shivam Jyoti and Aloke Saha, “Novel Approach to Design DPL-based Ternary Logic Circuits,” IEEE Electron Device Kolkata Conference 2018 (IEEE EDKCON-18), Kolkata, pp.- 631-635, 24-25 November 2018,	International	DOI Link
2019	Rahul Pal, Jayanta Ghosh and Aloke Saha, “Novel Self-Pipelining Strategy for Efficient Multiplications,” IEEE International Conference on Devices for Integrated Circuits (IEEE DevIC-2019), KGEC Kalyani, pp. 298-301, 23-24 March 2019.	International	DOI Link
2020	Marisha Gautam, Pratik Rajhans, Himanshu Kumar Verma, Ketan Dulwani, Ranojoy Chowdhury, Prerona Sanyal and Aloke Saha, “Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology,” IEEE National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA) 2020, pp. 1-3, 7-8 Feb. 2020.	National	DOI Link
2021	Rahul Pal, Rakesh Kumar Singh, Jayanta Ghosh and Aloke Saha, “Novel 9:1 Ternary Multiplexer on 32nm CMOS Technology,” International Conference on Devices for Integrated Circuits (DevIC-2021), KGEC Kalyani, 19-20 May 2021.	International	DOI Link
2022	Samanwita Mondal, Saptaparna Ghosh, Aditi Singha Mahapatra, Deblina Roy, Prerona Sanyal and Aloke Saha, “Novel 32nm CMOS Ternary Parity Generator-Checker,” IEEE International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON) 2022, 11-12 November 2022.	International	DOI Link
2023	Sudeshna Dutta, Snigdha Dutta, Osman Hossain Siddique, Rimpa Dey and Aloke Saha, "Novel 32nm CMOS Ternary 3's Complement Generator," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, pp. 87-91, 2023.	International	DOI Link
2023	Pradipta Sarkar, Anup Das and aloke saha, "One Dimensional Chaotic Map Implementation in FPGA Board for Image Encryption," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, pp. 48-51, 2023.	International	DOI Link

Book Chapter

Year	Book	DOI/Link/Web Link/UGC Link
2019	Rahul Raj, Rakesh Kumar Singh, Narendra Deo Singh, Saubhik Kumar and Aloke Saha, (2019). DPL-Based Novel 1-Trit Ternary Half-Subtractor. In: Kundu, S., Acharya, U., De, C., Mukherjee, S. (eds) Proceedings of the 2nd International Conference on Communication, Devices and Computing. Lecture Notes in Electrical Engineering, vol 602. Springer, Singapore.	DOI Link
2021	Somashree Chakraborty, Sonali Priya, Tripti Kumari, Saloni Thakur and Aloke Saha. (2022). MUX-Based Novel 9-trit CMOS Ternary Barrel Shifter. In: Sikdar, B., Prasad Maity, S., Samanta, J., Roy, A. (eds) Proceedings of the 3rd International Conference on Communication, Devices and Computing. Lecture Notes in Electrical Engineering, vol 851. Springer, Singapore.	DOI Link
2023	Shatabhisa Goswami, Ananya Mandal, Aishikee Mishra, Joyoshri Goswami,and Aloke Saha. (2023). Novel CMOS 1-Digit BCD-Adder Correction Circuit. In: Sarkar, D.K., Sadhu, P.K., Bhunia, S., Samanta, J., Paul, S. (eds) Proceedings of the 4th International Conference on Communication, Devices and Computing. ICCDC 2023. Lecture Notes in Electrical Engineering, vol 1046. Springer, Singapore.	DOI Link

Participations

Participation In Seminar / Conference / Symposium / Workshop / Discussion Meeting

SL. No.	Event	Duration	Year
1	ASIC-Physical Design and Verification using Mentor tool set	3 days	2020
2	Eradicating Cancer & Step Towards Healthy Life Style	1 day	2020
3	Journey from Vacuum Tube to Carbon Nanotube	1 day	2021
4	Analog and digital design flow using Mentor Graphics tool	1 day	2023
5	Training on “Red Hat Linux (RH033)”	22 days	2006
6	Workshop on Embedded System & DSP in VLSI	2 days	2007
7	Cadence Tools Training	2 days	2008
8	National workshop on Recent Trends in VLSI Design and Microelectronics	7 days	2009
9	NEN Foundation course	5 days	2009
10	International Conference on Devices & Communications (ICDeCom11) 2011	2 days	2011
11	Seminar on “Advances in Nano-Satellite Technology”	1 day	2015
12	IEEE Int. Conf. on Devices for Integrated Circuits(DevIC-2017)	2 days	2017
13	Seminar on “Teaching and Learning Skill Development”	1 day	2019
14	19th ACM Conference on Embedded Networked Sensor Systems (SenSys 2021)	4 days	2021
15	Trends of Modern Communication Engineering Systems	3 days	2020

Participation In Faculty Development Programmes

SL. No.	Name	Type	Duration
1	Introduction to Machine Learning	online	22.01.2022 to 25.01.2022
2	Applications of Machine Learning	online	22.02.2022 to 26.02.2022
3	Metamaterial and metamaterial assisted vacuum Electronic Devices	online	29.05.2023 to 02.06.2023
4	Fast Emerging Research Domain for Future Trends of Advanced Computation	online	06.02.2023 to 10.02.2023
5	Recent Advancement in Smart Grid and Renewable Energy	online	19.12.2022 to 23.12.2023
6	Recent Trends and Advances in Electronics	online	19.09.2022 to 23.09.2022

Thesis Supervised

Ph.D

SL. No.	Year	Topic	status	Rollno	University Registration	Affiliation
1	2018	Investigations on Low Power Solutions for Digital Circuits	Registered	Rahul Pal / 185EC10	NIT Patna

Post Graduate

SL. No.	Year	Topic	Rollno	University Registration	Affiliation
1	2011	Design of 8b × 8b Multiplier using delay equalisation in 0.18 µm CMOS Technology	Santimoy Mondal (Roll No. 09120099011)	MAKAUT	Dr. B. C. Roy Engineering College
2	2012	Novel Self-Pipelined Decomposition based Wallace Tree multiplier for low power application	Rahul Pal (Roll No. 12009910017)	MAKAUT	Dr. B. C. Roy Engineering College
3	2012	High-speed, power-efficient 8-bit square root circuit in TSMC 0.18µm CMOS Technology	Sankalita Pal (Roll No. 09120099017)	MAKAUT	Dr. B. C. Roy Engineering College
4	2013	Design of low power ±0.9V DPCCII- based RMS Detector for low frequency low voltage applications	Anwesa Sanphui (Roll No. 12009911007)	MAKAUT	Dr. B. C. Roy Engineering College
5	2014	Novel multi input compressors based 8×8 bit parallel multiplier	Vikas Kumar (Roll No. 12020412003)	MAKAUT	Dr. B. C. Roy Engineering College
6	2014	High precision 8-bit square root decoder	Charu Hashi Rena (Roll No. 12020412001)	MAKAUT	Dr. B. C. Roy Engineering College
7	2020	Design of novel Ternary Encryptor and decryptor using DPL for Secure Digital Transmission	Prerona Sanyal (Roll No. 12013518001)	MAKAUT	Dr. B. C. Roy Engineering College

Highlights

Faculty-Details