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(0343)-2501353,2504106
Mob: +91-6297128554 | Email: info@bcrec.ac.in
CALL US
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26-02-2009 |
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ECE |
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184948 |
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HINDUISM |
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1-445173085 |
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14-07-2006 |
| Teaching | Research | Industry |
|---|---|---|
| 214 | 208 | 0 |
| Date | Title | Journal | DOI | Link |
|---|---|---|---|---|
| 28-07-2025 | Novel, robust and efficient CMOS double-base adder | International Journal of Electronics Letters | DOI | View |
| 30-04-2025 | New Scalable 32ânm CMOS Radix-3 Priority Encoder | IETE Journal of Research | DOI | View |
| 28-04-2025 | Two dimensional chaotic scheme for image encryption in FPGA | Analog Integrated Circuits and Signal Processing | DOI | View |
| 16-06-2024 | Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder | IETE Journal of Research | DOI | View |
| 25-04-2024 | Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor | IETE Journal of Research | DOI | View |
| 15-03-2024 | Efficient 3's Complement Circuit for Ternary-ALU | Journal of Integrated Circuits and Systems | DOI | View |
| 25-05-2022 | Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer | Micro and Nanosystems, Bentham Science Publication | DOI | View |
| 25-11-2021 | Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier | Microelectronics Journal, Elsevier | DOI | View |
| 12-02-2021 | Efficient ternary comparator on CMOS technology | Microelectronics Journal, Elsevier | DOI | View |
| 01-12-2020 | Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication | Micro and Nanosystems, Bentham Science Publication | DOI | View |
| 09-07-2020 | DPL-Based Novel CMOS 1-Trit Ternary Full-Adder | International Journal of Electronics (IJE), Taylor & Francis | DOI | View |
| 20-03-2020 | Systematic Design Strategy for DPL-based Ternary Logic Circuit | International Journal of Nanoparticles (IJNP), Inderscience | DOI | View |
| 11-09-2019 | DPL-Based Novel Time Equalized CMOS Ternary-to-Binary Converter | International Journal of Electronics (IJE), Taylor & Francis | DOI | View |
| 24-08-2018 | Novel CMOS Multi-bit Counter for Speed-Power Optimization in Multiplier Design | AEU-International Journal of Electronics & Communication (IJEC), Elsevier | DOI | View |
| 26-05-2018 | DPL-Based Novel Binary-to-Ternary Converter on CMOS Technology | AEU-International Journal of Electronics & Communication (IJEC), Elsevier | DOI | View |
| 26-04-2017 | LPHS Logic Evaluation on TSMC 0.18”m CMOS Technology | International Journal of High Speed Electronics & Systems (IJHSES) | DOI | View |
| 21-04-2016 | Benchmarking of DPL Based 8bĂ8b Novel Wave-Pipelined Multiplier | International Journal of Electronics Letter | DOI | View |
| 01-05-2013 | Low power 6-GHz wave-pipelined 8bĂ8b multiplier | IET Circuits, Devices & Systems | DOI | View |
| Date | Title | Conference | DOI | Link |
|---|---|---|---|---|
| 29-05-2025 | Low-PDP 7:3-Counter with Novel Multi-threshold 2:1-Multiplexer | 2025 IEEE Devices for Integrated Circuit (DevIC) | DOI | View |
| 13-02-2025 | Chaotic Image Encryption Scheme Implemented in FPGA for Security Enhance | IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) | DOI | View |
| 13-02-2025 | Novel Sign-Magnitude Binary to Balanced-Ternary Encoder on Basys3 Artix7 FPGA | IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) | DOI | View |
| 25-11-2024 | Novel Low-PDP CMOS Double-Base Comparator | IEEE International Conference on Smart Power Control and Renewable Energy (ICSPCRE) | DOI | View |
| 29-07-2024 | Power Efficient Novel CMOS Double-base to Binary Encoder (DBE) | IEEE International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) | DOI | View |
| 29-05-2023 | Novel 32nm CMOS Ternary 3âs Complement Generator | 2023 IEEE Devices for Integrated Circuit (DevIC) | DOI | View |
| 29-05-2023 | One Dimensional Chaotic Map Implementation in FPGA Board for Image Encryption | 2023 IEEE Devices for Integrated Circuit (DevIC) | DOI | View |
| 10-04-2023 | Novel 32nm CMOS Ternary Parity Generator-Checker | 2022 International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON) | DOI | View |
| 21-06-2021 | Novel 9:1 Ternary Multiplexer on 32nm CMOS Technology | IEEE International Conference on Devices for Integrated Circuits (DevIC-2021) | DOI | View |
| 18-06-2020 | Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology | 2020 National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA) | DOI | View |
| 01-08-2019 | Novel Self-Pipelining Strategy for Efficient Multiplications | IEEE International Conference on Devices for Integrated Circuits (IEEE DevIC-2019), | DOI | View |
| 25-07-2019 | Novel Approach to Design DPL-based Ternary Logic Circuits | IEEE Electron Device Kolkata Conference 2018 (IEEE EDKCON-18) | DOI | View |
| 19-10-2017 | Study on LP-HS Logic for High Performance Digital Applications | IEEE International Conference on Devices for Integrated Circuits (DevIC-2017), | DOI | View |
| 24-03-2011 | Novel high speed MCML 8-bit by 8-bit multiplier | IEEE International Conference on Devices & Communications (ICDeCom-11), | DOI | View |
| Date | Title | Book Title | Editor | ISBN | DOI | Link |
|---|---|---|---|---|---|---|
| 01-05-2026 | Multi-Threshold 2:1-Multiplexer-Based Novel UT-Vedic 4 Ă4-Bit Multiplier | Next-Generation High-Speed Electronics and Optoelectronics | Aritra Acharyya, Angsuman Sarkar, Mariya Aleksandrova | ISBN 978-981-95-3892-8 | DOI | View |
| 28-07-2023 | Novel CMOS 1-Digit BCD-Adder Correction Circuit | Lecture Notes in Electrical Engineering | Dilip Kumar Sarkar, Pradip Kumar Sadhu, Sunandan Bhunia, Jagannath Samanta, Suman Paul | Online ISBN 978-981-99-2710-4 | DOI | View |
| 18-02-2022 | MUX-Based Novel 9-trit CMOS Ternary Barrel Shifter. | Lecture Notes in Electrical Engineering | Biplab Sikdar, Santi Prasad Maity, Jagannath Samanta, Avisankar Roy | Online ISBN 978-981-16-9154-6 | DOI | View |
| 17-12-2019 | DPL-Based Novel 1-Trit Ternary Half-Subtractor | Lecture Notes in Electrical Engineering | Sumit Kundu, U. Shripathi Acharya, Chanchal Kr. De, Surajit Mukherjee | Online ISBN 978-981-15-0829-5 | DOI | View |
| Committee Name | Start Date | End Date |
|---|---|---|
| INSTITUTE INNOVATION COUNCIL | 01-07-2025 | 03-06-2026 |
| PROJECT COMMITTE | 13-06-2024 | 03-06-2026 |
| DEPARTMENTAL DISCIPLINARY COMMITTEE | 02-04-2024 | 03-06-2026 |
| DEPARTMENTAL SEMINAR WORKSHOP ORGANIZING COMMITTEE | 02-04-2024 | 03-06-2026 |
| Project Name | Start Date | End Date | Funded | Funding Agency | Agency Type | Role | Sanction Letter |
|---|---|---|---|---|---|---|---|
| Upgradation and modernization of the VLSI Lab (Phase II) to strengthen advanced teaching, hands-on training, and research in front-end and back-end VLSI design. The project focuses on updated EDA tools, enhanced FPGA/ASIC prototyping facilities, and an industry-aligned workflow environment. The objective is to build a robust ecosystem that supports UG/PG learning and faculty-led research in the VLSI domain. | 12-01-2022 | 11-01-2024 | Yes | government | Member | Yes |