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Dr. ALOKE  SAHA

Associate Professor

About

aloke.saha@bcrec.ac.in

1981-01-02

2009-02-26

Electronics and Communication Engineering

Flat-2B; Mira Enclave; Sarat Pally; Fuljhore; Durgapur; West Bengal- 713206

184948

Efficient higher-radix and multi-base logic development with unconventional (i.e. MTCMOS, Memristor, CNTFET etc.)/Hybrid strategies for next generation smart processing, Low PDP solution for digital circuits/system, ASIC for data security, Adaptive scalable digital architecture, floating point circuit/system, Reversible Circuit design etc.

Qualifications

Educational Qualifications
  • PhD
  • BIT Mesra - 2015
  • M.E
  • BIT Mesra - 2006
  • B.Tech
  • University of Kalyani - 2003
Examination Cleared
  • GATE
Teaching and R & D experience
Teaching Research Industry
17.5 Years 15.5 Years

Associate Professor at Dr. B. C. Roy Engineering College (01.07.2022 to present)

Assistant Professor (AGP 8000) at Dr. B. C. Roy Engineering College (26.02.2009 to 30.06.2022)

Lecturer at BIT Mesra (16.07.2006 to 25.02.2009)

BE/B.Tech : Digital System Design, CMOS VLSI Design, Analog Electronic Circuits, VLSI Circuit & Systems, EDA for VLSI Design, Embedded System, Basic Electronics, Microelectronics & VLSI Design, Digital Signal Processing, Analog Communication, Microelectronics Engineering, Semiconductor Devices, Pulse & Digital Circuits (PDC)

M.E/M.Tech: Digital IC Design, Processor Architecture for VLSI, Advanced VLSI Design, Mobile communication, Embedded System

Efficient higher-radix and multi-base logic development with unconventional (i.e. MTCMOS, Memristor, CNTFET etc.)/Hybrid strategies for next generation smart processing, Low PDP solution for digital circuits/system, ASIC for data security, Adaptive scalable digital architecture, floating point circuit/system, Reversible Circuit design etc.

Finance-chair: MESIICON 2022, NCETSTEA-2020

Session Chair: ICCDC-2023

Entrepreneurship Week-India 2010 Championship Runner-up by National Entrepreneurship Network, India 2010.

Innovative project award in Master of Engineering by Cadence Design Systems (I) Pvt. Ltd.(Cadence Design Contest 2005-2006)

Activities

Membership of professional bodies
SL. No. Professional Body
1 Member IEEE (Since 2015): Member Number 93689053 Reviewer (Journal): IET Computer & Digital Technique, IET Circuits Devices & Systems, International Journal of Electronics (IJE)-Taylor & Francis, International Journal of Electronics & Communication (IJEC)-Elsevier, Journal of supercomputing-Springer, Journal of Electrical and Computer Engineering, Journal of Integrated Circuits & Systems etc. Reviewer (Conference) : IEEE International Symposium on Circuits and Systems (ISCAS), International Conference on Communication, Devices & Computing (ICCDC)- Springer, IEEE MESIICON 2022, IEEE NCETSTEA-2020 etc. Technical Committee Member: ICCDC-2023, ICCDC-2021, ICCDC-2019.
Project Ideas Submitted to Govt. Agencies/ On-going Projects / Research Ideas under preparation & execution
SL. No. Project Ideas Submitted to Govt. Agencies
1 On-going Project: 1. Up-gradation & Modernization of "VLSI Lab (Phase-ll)" to enhance teaching, training and research capabilities in VLSI domain Total Project Cost: Rs. 13,87,500/- Sanctioning Authority/duration: AICTE/2-years

Publications

Journal
Date Title Journal DOI Link
28-04-2025 Two dimensional chaotic scheme for image encryption in FPGA Analog Integrated Circuits and Signal Processing DOI View
16-06-2024 Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder IETE Journal of Research DOI View
25-04-2024 Novel Single-Step 32nm-CMOS Hardware T-Encryptor/Decryptor IETE Journal of Research DOI View
15-03-2024 Efficient 3's Complement Circuit for Ternary-ALU Journal of Integrated Circuits and Systems DOI View
25-05-2022 Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer Micro and Nanosystems, Bentham Science Publication DOI View
25-11-2021 Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier Microelectronics Journal, Elsevier DOI View
12-02-2021 Efficient ternary comparator on CMOS technology Microelectronics Journal, Elsevier DOI View
01-12-2020 Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication Micro and Nanosystems, Bentham Science Publication DOI View
09-07-2020 DPL-Based Novel CMOS 1-Trit Ternary Full-Adder International Journal of Electronics (IJE), Taylor & Francis DOI View
20-03-2020 Systematic Design Strategy for DPL-based Ternary Logic Circuit International Journal of Nanoparticles (IJNP), Inderscience DOI View
11-09-2019 DPL-Based Novel Time Equalized CMOS Ternary-to-Binary Converter International Journal of Electronics (IJE), Taylor & Francis DOI View
24-08-2018 Novel CMOS Multi-bit Counter for Speed-Power Optimization in Multiplier Design AEU-International Journal of Electronics & Communication (IJEC), Elsevier DOI View
26-05-2018 DPL-Based Novel Binary-to-Ternary Converter on CMOS Technology AEU-International Journal of Electronics & Communication (IJEC), Elsevier DOI View
26-04-2017 LPHS Logic Evaluation on TSMC 0.18µm CMOS Technology International Journal of High Speed Electronics & Systems (IJHSES) DOI View
21-04-2016 Benchmarking of DPL Based 8b×8b Novel Wave-Pipelined Multiplier International Journal of Electronics Letter DOI View
01-05-2013 Low power 6-GHz wave-pipelined 8b×8b multiplier IET Circuits, Devices & Systems DOI View
Conference
Date Title Conference DOI Link
24-03-2011 Novel high speed MCML 8-bit by 8-bit multiplier IEEE International Conference on Devices & Communications (ICDeCom-11), DOI View
19-10-2017 Study on LP-HS Logic for High Performance Digital Applications IEEE International Conference on Devices for Integrated Circuits (DevIC-2017), DOI View
25-07-2019 Novel Approach to Design DPL-based Ternary Logic Circuits IEEE Electron Device Kolkata Conference 2018 (IEEE EDKCON-18) DOI View
01-08-2019 Novel Self-Pipelining Strategy for Efficient Multiplications IEEE International Conference on Devices for Integrated Circuits (IEEE DevIC-2019), DOI View
18-06-2020 Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology 2020 National Conference on Emerging Trends on Sustainable Technology and Engineering Applications (NCETSTEA) DOI View
21-06-2021 Novel 9:1 Ternary Multiplexer on 32nm CMOS Technology IEEE International Conference on Devices for Integrated Circuits (DevIC-2021) DOI View
10-04-2023 Novel 32nm CMOS Ternary Parity Generator-Checker 2022 International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON) DOI View
29-05-2023 Novel 32nm CMOS Ternary 3‘s Complement Generator 2023 IEEE Devices for Integrated Circuit (DevIC) DOI View
29-05-2023 One Dimensional Chaotic Map Implementation in FPGA Board for Image Encryption 2023 IEEE Devices for Integrated Circuit (DevIC) DOI View
Book Chapters
Date Title Book Title Editor ISBN DOI Link
17-12-2019 DPL-Based Novel 1-Trit Ternary Half-Subtractor Lecture Notes in Electrical Engineering Sumit Kundu, U. Shripathi Acharya, Chanchal Kr. De, Surajit Mukherjee Online ISBN 978-981-15-0829-5 DOI View
18-02-2022 MUX-Based Novel 9-trit CMOS Ternary Barrel Shifter. Lecture Notes in Electrical Engineering Biplab Sikdar, Santi Prasad Maity, Jagannath Samanta, Avisankar Roy Online ISBN 978-981-16-9154-6 DOI View
28-07-2023 Novel CMOS 1-Digit BCD-Adder Correction Circuit Lecture Notes in Electrical Engineering Dilip Kumar Sarkar, Pradip Kumar Sadhu, Sunandan Bhunia, Jagannath Samanta, Suman Paul Online ISBN 978-981-99-2710-4 DOI View

Participations

Participation In Seminar / Conference / Symposium / Workshop / Discussion Meeting

SL. No. Event Duration Year
1 ASIC-Physical Design and Verification using Mentor tool set 3 days 2020
2 Eradicating Cancer & Step Towards Healthy Life Style 1 day 2020
3 Journey from Vacuum Tube to Carbon Nanotube 1 day 2021
4 Analog and digital design flow using Mentor Graphics tool 1 day 2023
5 Training on “Red Hat Linux (RH033)” 22 days 2006
6 Workshop on Embedded System & DSP in VLSI 2 days 2007
7 Cadence Tools Training 2 days 2008
8 National workshop on Recent Trends in VLSI Design and Microelectronics 7 days 2009
9 NEN Foundation course 5 days 2009
10 International Conference on Devices & Communications (ICDeCom11) 2011 2 days 2011
11 Seminar on “Advances in Nano-Satellite Technology” 1 day 2015
12 IEEE Int. Conf. on Devices for Integrated Circuits(DevIC-2017) 2 days 2017
13 Seminar on “Teaching and Learning Skill Development” 1 day 2019
14 19th ACM Conference on Embedded Networked Sensor Systems (SenSys 2021) 4 days 2021
15 Trends of Modern Communication Engineering Systems 3 days 2020
Faculty Development Programmes
Start Date End Date Title Organizer
05-12-2007 06-12-2007 Workshop on Embedded System & DSP in VLSI Department of ECE, NIT Rourkela
04-01-2009 10-01-2009 National workshop on Recent Trends in VLSI Design and Microelectronics Department of ECE, Bengal Engineering & Science University (BESU) Shibpur
20-07-2009 24-07-2009 NEN Foundation course NEN Education, Bangalore
14-03-2015 15-03-2015 Workshop on Microwave Engineering & Applications (MEA-2015) Dr. B. C. Roy Engineering College
15-05-2019 17-05-2019 Hands on training on “Full-custom VLSI Design using Mentor Graphics” by CorEL Technologies (I) Pvt. Ltd. Bengaluru ECE Department, Dr. B. C. Roy Engineering College, Durgapur
07-05-2020 09-05-2020 ASIC - Physical Design and Verification using Mentor toolset Sandeepani School of Embedded System Design, Bangalore
18-09-2020 20-09-2020 Trends of Modern Communication Engineering Systems Electronics and Communication Engineering Department, BCREC and IEEE student branch BCREC
22-01-2022 25-01-2022 FDP on Introduction to Machine Learning Mechanical Engineering Department of Dr.B.C. Roy Engineering College
22-02-2022 26-02-2022 Applications of Machine Learning Department of CSE and Nodal Centre, Zone-II, MAKAUT

Thesis Supervised

Ph.D
SL. No. Year Topic status Rollno University Registration Affiliation
1 2018 Investigations on Low Power Solutions for Digital Circuits Registered
Rahul Pal / 185EC10
 NIT Patna
Post Graduate
SL. No. Year Topic Rollno University Registration Affiliation
1 2011 Design of 8b × 8b Multiplier using delay equalisation in 0.18 µm CMOS Technology
Santimoy Mondal (Roll No. 09120099011)
 MAKAUT Dr. B. C. Roy Engineering College
2 2012 Novel Self-Pipelined Decomposition based Wallace Tree multiplier for low power application
Rahul Pal (Roll No. 12009910017)
 MAKAUT Dr. B. C. Roy Engineering College
3 2012 High-speed, power-efficient 8-bit square root circuit in TSMC 0.18µm CMOS Technology
Sankalita Pal (Roll No. 09120099017)
 MAKAUT Dr. B. C. Roy Engineering College
4 2013 Design of low power ±0.9V DPCCII- based RMS Detector for low frequency low voltage applications
Anwesa Sanphui (Roll No. 12009911007)
 MAKAUT Dr. B. C. Roy Engineering College
5 2014 Novel multi input compressors based 8×8 bit parallel multiplier
Vikas Kumar (Roll No. 12020412003)
 MAKAUT Dr. B. C. Roy Engineering College
6 2014 High precision 8-bit square root decoder
Charu Hashi Rena (Roll No. 12020412001)
 MAKAUT Dr. B. C. Roy Engineering College
7 2020 Design of novel Ternary Encryptor and decryptor using DPL for Secure Digital Transmission
Prerona Sanyal (Roll No. 12013518001)
 MAKAUT Dr. B. C. Roy Engineering College

Patent

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