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DR. SOUMEN  MALLICK

Assistant Professor

About

soumen.mallick@bcrec.ac.in

1982-01-01

2010-08-11

Electrical Engineering

CD-16/1, M.A.M.C Township, V. K. Nagar, Durgapur, West Bardhhaman, PIN-713210.

187682

I received B-Tech degree from Haldia Institute of Technology, Haldia, West Bengal, India in 2004. I received M-Tech degree from Jadavpur University, Jadavpur, West Bengal, India in 2007. I received my PhD degree from NIT Durgapur, West Bengal, India in 2019. Since 2010, I am working as an assistant professor (III) in the department of Electrical Engineering, Dr. B. C. Roy Engineering College, Durgapur, West Bengal, India. In addition to that, photography and driving is my passion.

Analog and Digital VLSI circuits, Meta-Heuristic Optimization Techniques

Qualifications

Educational Qualifications
  • HS
  • Simlapal Madan Mohan High School - 2000
  • B-Tech
  • Haldia Institute of pTechnology - 2004
  • M-Tech
  • Jadavpur University - 2007
  • PhD
  • NIT Durgapur - 2019
Examination Cleared
  • GATE
Teaching and R & D experience
Teaching Research Industry
18 Years 9 Years 0 Year

Till now 18 years of experience in teaching and research.

Analog and Digital VLSI circuits, Meta-Heuristic Optimization Techniques

Activities

Area of Interest

Analog and digital VLSI design, Optimization, Meta-Heuristic techniques

Expertise

He completed his B.Tech degree in Instrumentation Engineering from Haldia Institute of Technology in 2004. He received his M.Tech degree in VLSI Design & Microelectronics Technology from Jadavpur University in 2007. He received his Ph. D degree from National Institute of Technology, Durgapur in 2019. His research area is Analog & Digital VLSI design and optimization using different Evolutionary Optimization Techniques.

Publications

Journal
Date Title Journal DOI Link
24-02-2022 Optimal design of second generation current conveyor using craziness-based particle swarm optimisation International Jounal of Bio-Inspired Computation DOI View
05-06-2017 SEOA based optimal design of analogue CMOS amplifier circuits International Journal of Bio-Inspired Computation DOI View
10-02-2017 Optimal sizing of CMOS analog circuits using gravitational search algorithm with particle swarm optimization International Journal of Machine Learning and Cybernetics DOI View
03-07-2016 CMOS analogue amplifier circuits optimization using hybrid backtracking search algorithm with differential evolution Journal of Experimental & Theoretical Artificial Intelligence DOI View
02-03-2016 Optimal sizing and design of CMOS analogue amplifier circuits using craziness-based particle swarm optimization International Journal of Numerical Modelling: Electronic Networks, Devices and Fields DOI View
Conference
Date Title Conference DOI Link
24-11-2016 CMOS analog amplifier circuit sizing using opposition based harmony search algorithm 2016 International Conference on Communication and Signal Processing (ICCSP) DOI View
23-10-2017 Optimal design of 5.5 GHz CMOS LNA using hybrid fitness based adaptive De with PSO 2017 International Electrical Engineering Congress (iEECON2017) DOI View
23-10-2017 Sizing of two stage Op-Amp using OHS algorithm 2017 International Electrical Engineering Congress (iEECON) DOI View
01-12-2024 Automated Design of CMOS-DACML Circuit 2024 IEEE International Conference on Communication Computing and Signal Processing (ICCCS) DOI View
23-04-2025 A DVCC based Realization of Optimized Fractional Step Low Pass Filter IEEE International Conference on Emerging Trends in Engineering and Medical Sciences DOI View
Book Chapters
Date Title Book Title Editor ISBN DOI Link
23-08-2018 Optimal Design of 2.4 GHz CMOS LNA Using PSO with Aging Leader and Challenger Advances in Intelligent Systems and Computing Bhatia, S., Tiwari, S., Mishra, K., Trivedi, M. 978-981-13-0341-8 DOI View

Participations

Thesis Supervised

Patent

Patents
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